摘要 :
Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are s...
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Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffer''s foot voltage enable sub-T4 write and read without degrading the bit-cell''s density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 muW in leakage power.
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摘要 :
A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica sche...
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A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.
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摘要 :
This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ¿m2 six-transistor bitcell that supports a broa...
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This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ¿m2 six-transistor bitcell that supports a broad range of operating voltages for low-power and high-frequency embedded applications. The tileable 128 kb SRAM subarray achieves 72% array efficiency with 4.2 Mb/mm2 bit density, and consumes 5 mW of leakage power at the supply voltage of 1 V. The design provides 4 GHz and 2 GHz of operating frequencies at the supply voltages of 1.0 V and 0.8 V, respectively. The integrated power management scheme features close-loop memory array leakage control, floating bitline, and wordline driver sleep transistor, resulting in a 58% reduction in subarray leakage power consumption.
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摘要 :
Recent advances in portable and wearable electroencephalograph (EEG) devices has raised the need to detect emotions in real time for applications such as wellbeing monitoring, gaming and social networking. A number of researchers ...
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Recent advances in portable and wearable electroencephalograph (EEG) devices has raised the need to detect emotions in real time for applications such as wellbeing monitoring, gaming and social networking. A number of researchers have reported real time emotion detection systems implemented on a computer. This study advances these efforts by implementing a real time emotion detection system on a wirelesses sensor node with minimal hardware resources (256 kb of flash memory and 16 MHz processing speed) suitable for integration in a wearable wireless sensor node. The experimental results demonstrate that detecting emotions within the sensor node using suitable algorithms prolong the battery life by 5 days (38%) and by 39 days at an emotion detection rate of 2 and 60 s, respectively, as compared with transmitting the raw EEG data wirelessly. This also reduces the length of packets transmitted which directly minimises the packet error rate and the power that would be consumed because of retransmission of these erroneous packets.
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摘要 :
In thermally assisted switching-magnetic random access memory (TAS-MRAM), a storage layer is pinned by exchange bias with an antiferromagnet, and is unpinned during writing because of a heating pulse of current injected through th...
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In thermally assisted switching-magnetic random access memory (TAS-MRAM), a storage layer is pinned by exchange bias with an antiferromagnet, and is unpinned during writing because of a heating pulse of current injected through the junction. The current densities used for heating are of the order of magnitude of the current densities at which spin-transfer torque (STT) acts as an effective field from the point of view of the thermal activation model. To seek for such combined influence of heating and STT in TAS-MRAM, statistical writing tests were performed on 1-kb test devices. The phase diagrams with the pinned and unpinned regions were obtained. A reduction of the writing field in the unpinned region was evidenced by changing the polarity, which is asymmetrical with respect to the direction of writing. This is consistent with STT influence. The order of magnitude of the effect is in good agreement with previous work on writing field dependence with the current and compares well with numerical estimates using the Neel-Brown-modified model to consider the STT effect. The writing field can be reduced by 15% by properly choosing the current direction for a current density of 2 MA/cm.
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摘要 :
Recent high-speed digital-to-analogue converters (DACs) cannot be easily characterised at their highest rate because of the very high cost of commercially available bit-error rate testers at the required DACs rate. Among possible ...
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Recent high-speed digital-to-analogue converters (DACs) cannot be easily characterised at their highest rate because of the very high cost of commercially available bit-error rate testers at the required DACs rate. Among possible solutions, an inexpensive approach is the use of a multiplexer (MUX) with built-in memory to provide the required bit stream for one input bit of the DAC. This work presents a half-rate 32 GSps MUX with 1 kbit built-in memory as a part of an arbitrary test signal generator for a DAC. The proposed system can be used to test DACs developed for future OFDM optical communications. Here, a bipolar-CMOS (BiCMOS) 0.25 μm SiGe process is utilised. One challenge is to optimise the power dissipation of such an MUX which requires employing several techniques. At the system level, the conventional tree structure was avoided because of the high number of latches required to re-time the clock and data signals. At the highest rates, a multiphase-clock architecture was utilised which halves the number of latches compared with a tree structure. The phase margin of the multiphase-clock structure is enhanced in this work. At lower rates, a one-stage MUX architecture was used which also halves the number of latches. Additionally, the latency between the analogue-digital interface is discussed. All the implemented circuits including the biasing of the whole chip and its routing are presented. The design and optimisation of the clock driver for low-power functionality is discussed. Measurement results show proper operation at 32 GSps. The total power dissipation is 875 mW, which is the lowest power among the designs usable for DAC testing and at the same rate class.
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